Not legally an Engineer Yet, Call me an EIT
I am finishing my PhD in Electrical Engineering and expect to complete it within the year. I am eager to transition into industry and apply my expertise to real-world challenges. My background spans Embedded System Design, Chip Design, FPGA Programming, and Full-Stack Web Development. However, my greatest strength lies in quickly adapting to new technologies and applying them effectively.
I am seeking a role where I can contribute meaningfully while completing my degree, with the goal of leveraging my skills in a dynamic and practical environment.
Explore my research and development work on my GitHub and Google Scholar.
| Category | Details |
|---|---|
| Chip Design | - Tools: Cadence Virtuoso, Magic, XScheme, NGSpice |
| - Technologies: AMS 350nm, TSMC 130nm, Skywater 180nm | |
| - Achievements: Designed multiple tapeouts, including AMS 350nm and Skywater 180nm | |
| PCB Design | - Tools: DipTrace, Altium, KiCad |
| - Experience: Analog and Digital Designs, Schematic to Layout | |
| FPGA Programming | - Platforms: Xilinx, Altera, Trion Chips |
| - Languages: VHDL, SystemVerilog, Verilog | |
| - Achievements: Developed FPGA labs for ENEL 453, co-instructed multiple sessions | |
| Embedded Systems | - Platforms: AVR, ARM chips |
| - Languages: C, C++, Python (MicroPython & CircuitPython) | |
| Linux Distributions | - Red Hat, Ubuntu (Server and Workstation Variants) |
| System Administration | - Tools: Ansible, Ceph, Hyper-V, Proxmox, Docker |
| Cloud Providers | - Google Cloud, Amazon Web Services, DigitalOcean, IBM Cloud |
| Web Programming | - Languages & Frameworks: Python (Flask), JavaScript (Node.js), C# (.NET) |
| Other Skills | - Buildbot, Soldering, Oscilloscope, Vector Network Analyzer, Computer Maintenance |
University of Calgary, Alberta
Programming Intern
Eideticom (500 Hours)
Lab Assistant Director
University of Calgary, I2Sense Laboratory (May 2019 – May 2025)
Distribution Powerline Designer - Undergraduate Internship
ATCO Electric (Jan 2017 – Dec 2017)