Resume, Projects, Blog

I’m in the final year of my PhD working on finalizing my research in CMOS Image Sensors. I’ll be looking for work in the coming year. I have experience in chip design, FPGA programming, and system architecting for hardware and software projects. Please check out my research and development on my github and published papers.

TOOL FAMILIARITY

• Chip Design: Cadence Virtuoso, Magic & XScheme (AMS 350nm, TSMC 130nm, Skywater 180nm)
• PCB Design: Diptrace, Altium, KiCad (Various Analog and Digital Boards)
• FPGA Programming: Xilinx and Altera Chips, Programmed in VHDL, System Verilog, and Verilog
• Embedded Systems: AVR and ARM chips, Programmed in C, C++, and Python (Circuit Python)
• Linux Distributions RedHat, Ubuntu
• System Administration Ansible, Ceph Storage Clustering, Hyper V, Proxmox
• Cloud Providers Google Cloud, Amazon Web Services, Digital Ocean
• Other: Buildbot, Soldering, Oscilloscope, Vector Network Analyser, Computer Maintenance

EDUCATION

• University of Calgary, Alberta
  • BSc. With Honors (2019)
  • PhD. (2019 – Expected Graduation October 2024)
    • Transferred Directly from MSc. To PhD May 2020

TRAINING

• EDx Contract Law Course (Apr 2020)
• EDx Introduction to Cloud Computing (Aug 2021)
• Cadence Training Modules (2020)
• Adobe Creative Cloud Training (2020)

EXPERIENCE

• Programming Internship Eideticom (500 Hours)
  • Worked at [Eideticom] (https://www.eideticom.com/) on testing and validation
  • Worked with buildbot writing hardware tests, updating an existing python codebase
• PhD. Thesis with Research (May 2019 – Expected Graduation 2024)
  • University of Calgary, I2Sense Laboratory
  • Research focus: High-Speed Wide Dynamic Range CMOS sensors
  • Lab management responsibilities (safety, licensing, equipment, marketing)
• Distribution Powerline Designer (Jan 2017 – Dec 2017)
  • ATCO Electric
  • Performed price estimation and design for power distribution projects in Alberta

Memberships

• Apega Membership (EIT)
• IEEE Membership