Not legally an Engineer Yet, Call me an EIT
I’ve used a handful of different VLSI processes and so I figured it might be worth to note a few of their quirks. VLSI being Very large scale integration, more collequially called silicon design much to the great upset of anyone who designs their materials in GaAs or other semi-conductors beyond the narrow world of silicon. My main design tools have been the Cadence suite of tools, and the open source XScheme + Magic combination. Of the two I’d say that I like XScheme + Magic substantially more and would choose them preferentially assuming that a given kit is able to be run on them. This then becomes the major upset as most kits are sadly setup with versions only to support the massively expensive paid tools. XScheme + Magic may have issues; however, it’s free. With the most basic barebones license to Cadence costing $50,000 you have to ask how many months of engineering time does it actually save you. It better save you at least 5 months if starting salaries in the VLSI industry are to be believed.
This was the first process that I used. Austrian Microsystems 350nm process is unique in the fact that it’s documentation is markedly better than any of the other processes I’ve tried. And talking with others it’s uniquely good across the processes they’ve tried as well. With a really good library of silicon verified components including current sources, op-amps, comparators, DACs, ADCs, and more. I completed two chip designs in this process and most of a third before Candece licensing issues finally became too much of a burden to bear. They’re honestly a really excellent process for rapid analog designs that don’t rely on high-speed. Also considering the lack of a pinned photodiode they have process options which provide comparatively great optical performance.
The dual poly process provides extremely convienent capacitors, as well as has their setup allowing certain elements in DRC which others prohibit.
I have done some design in both 350nm and 180nm; however, their 130nm process was used by a capstone team which I supervised extensively. TSMC is like the name brand VLSI process that most others seem to get compared to given their prevalence among every silicon company using them as a fabrication facility. The team ended up not having their needed access to the digital standard cells meaning they had to produce them themselves. This lead to a huge amount of additional work which I’m glad to say I didn’t have to handle. What I did have to assist with was the final design cleanup as their DRC recognized poly over non-implanted substrate as a DRC error, which given it’s convenience for routing made for an unfortunate week of continually adding implants in was which correct the errors without causing unintended overlaps. A minor rework of every cell they used.
SKY130 is the open source process. Technically I’ve done 4 different tapeouts in it; however, consideirng only one of those tapeouts involved analog design I’ll say I’ve done 1 tapeout here. It’s certainly a woefully underdocumented kit; however, that’s fairly par for the course with VLSI in general, so I’ll content myself with being grateful it exists at all. At some point I do need to properly doucment my Tiny Tapeout projects more fully. However some of that will definitely have to wait for now.